// scaller.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module scaller (
		input  wire       clk_clk,              //    clk.clk
		input  wire       reset_reset_n,        //  reset.reset_n
		input  wire [7:0] sink_data,            //   sink.data
		input  wire       sink_valid,           //       .valid
		input  wire       sink_startofpacket,   //       .startofpacket
		input  wire       sink_endofpacket,     //       .endofpacket
		output wire       sink_ready,           //       .ready
		output wire [7:0] source_data,          // source.data
		output wire       source_valid,         //       .valid
		output wire       source_startofpacket, //       .startofpacket
		output wire       source_endofpacket,   //       .endofpacket
		input  wire       source_ready          //       .ready
	);

	wire    rst_controller_reset_out_reset; // rst_controller:reset_out -> alt_vip_cl_scl_0:main_reset

	scaller_alt_vip_cl_scl_0 alt_vip_cl_scl_0 (
		.main_clock         (clk_clk),                        // main_clock.clk
		.main_reset         (rst_controller_reset_out_reset), // main_reset.reset
		.din_data           (sink_data),                      //        din.data
		.din_valid          (sink_valid),                     //           .valid
		.din_startofpacket  (sink_startofpacket),             //           .startofpacket
		.din_endofpacket    (sink_endofpacket),               //           .endofpacket
		.din_ready          (sink_ready),                     //           .ready
		.dout_data          (source_data),                    //       dout.data
		.dout_valid         (source_valid),                   //           .valid
		.dout_startofpacket (source_startofpacket),           //           .startofpacket
		.dout_endofpacket   (source_endofpacket),             //           .endofpacket
		.dout_ready         (source_ready)                    //           .ready
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                 // reset_in0.reset
		.clk            (clk_clk),                        //       clk.clk
		.reset_out      (rst_controller_reset_out_reset), // reset_out.reset
		.reset_req      (),                               // (terminated)
		.reset_req_in0  (1'b0),                           // (terminated)
		.reset_in1      (1'b0),                           // (terminated)
		.reset_req_in1  (1'b0),                           // (terminated)
		.reset_in2      (1'b0),                           // (terminated)
		.reset_req_in2  (1'b0),                           // (terminated)
		.reset_in3      (1'b0),                           // (terminated)
		.reset_req_in3  (1'b0),                           // (terminated)
		.reset_in4      (1'b0),                           // (terminated)
		.reset_req_in4  (1'b0),                           // (terminated)
		.reset_in5      (1'b0),                           // (terminated)
		.reset_req_in5  (1'b0),                           // (terminated)
		.reset_in6      (1'b0),                           // (terminated)
		.reset_req_in6  (1'b0),                           // (terminated)
		.reset_in7      (1'b0),                           // (terminated)
		.reset_req_in7  (1'b0),                           // (terminated)
		.reset_in8      (1'b0),                           // (terminated)
		.reset_req_in8  (1'b0),                           // (terminated)
		.reset_in9      (1'b0),                           // (terminated)
		.reset_req_in9  (1'b0),                           // (terminated)
		.reset_in10     (1'b0),                           // (terminated)
		.reset_req_in10 (1'b0),                           // (terminated)
		.reset_in11     (1'b0),                           // (terminated)
		.reset_req_in11 (1'b0),                           // (terminated)
		.reset_in12     (1'b0),                           // (terminated)
		.reset_req_in12 (1'b0),                           // (terminated)
		.reset_in13     (1'b0),                           // (terminated)
		.reset_req_in13 (1'b0),                           // (terminated)
		.reset_in14     (1'b0),                           // (terminated)
		.reset_req_in14 (1'b0),                           // (terminated)
		.reset_in15     (1'b0),                           // (terminated)
		.reset_req_in15 (1'b0)                            // (terminated)
	);

endmodule
